`include "C:\Users\lenovo\Desktop\Files\Linear_RISCV\LR_ver_0\src\include\include.vh"
module 	idu(
    input          clk,rst_n,
    
    input	[31:0] instr,

    input   [4:0]  rd_i,
    input   [63:0] Rd_i,    
    input          RegWrite_i,


    output  [5:0]  uop_code,
    output  [3:0]  exe_type,

    output	[4:0]  rd,
    output	[4:0]  rs1,
    output	[4:0]  rs2,
    
    output	[63:0] Rs1,
    output	[63:0] Rs2,
    
    output  [4:0]  ctrl_bus,
    
    output  [31:0] imm_o
);
    wire    [6:0]  funct7;
    wire    [6:0]  opcode;
    wire    [2:0]  funct3;
    divider inst_divider(
        instr,
        rd,rs1,rs2,
        opcode,
        funct7,
        funct3		
    );
    translater op_translater(
        opcode,
        funct7,
        funct3,
        exe_type,
        uop_code
    );
    Ctrl_gen Ctrl_gen_u(
        exe_type,
        ctrl_bus
    );

    Imm_gen imm_gen(
    	opcode,
        instr,
    	imm_o
    );
    RegFiles #(.zero ( 64'd0 ))
    inst_RegFiles (
        .clk               (clk),
        .rst_n             (rst_n),
        .RegWrite_i        (RegWrite_i),
        .rd_i              (rd_i),
        .rs1_i             (rs1),
        .rs2_i             (rs2),
        .Rd_i              (Rd_i),
        .Rs1_o             (Rs1),
        .Rs2_o             (Rs2)
    );

endmodule 

